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| nanoamp solutions, inc. 1982 zanker road, san jose, ca 95112 ph: 408-573-8878, fax: 408-573-8877 www.nanoamp.com nt5ds4m32eg doc # 14-02-045 rev a ecn 01-1118 1 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information 1m 32 bits 4 banks double data rate synchronous ram with bi-directional data strobe and dll general overview the nt5ds4m32eg is 134,217,728 bits of double data ra te synchronous dynamic ram organized as 4 x 1,048,576 bits by 32 i/os. synchronous features with data stro be allow extremely high performance up to 400mbps/pin. i/o transactions are possible on both edges of the clock. ra nge of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a vari ety of high performance me mory system applications. features ? vdd = 2.5v5% , vddq = 2.5v5% ? sstl_2 compatible inputs/outputs ? 4 banks operation ? mrs cycle with address key programs -cas latency 2,3 (clock) -burst length (2, 4, 8 and full page) -burst type (sequential & interleave) ? full page burst length fo r sequential burst type only ? start address of the full page burst should be even ? all inputs except data & dm are sampled at the ris- ing edge of the system clock ? differential clock input(ck & /ck) ? data i/o transaction on both edges of data strobe ? 4 dqs (1 dqs/byte) ? dll aligns dq and dqs transaction with clock transaction ? edge aligned data & data strobe output ? center aligned data & data strobe input ? dm for write masking only ?auto & self refresh ? 32ms refresh period (4k cycle) ? 144-ball fbga package ? maximum clock frequency up to 200mhz ? maximum data rate up to 400mbps/pin ordering information part number package operating temperature max. frequency max data rate interface cl = 3 cl = 2 NT5DS4M32EG-5g 144-balls green fbga 0 - 70 c 200mhz 111mhz 400mbps/pin NT5DS4M32EG-5 200mhz - 400mbps/pin sstl_2 nt5ds4m32eg-6 166mhz - 333mbps/pin
doc # 14-02-045 rev a ecn 01-1118 2 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information figure 1: pin conf iguration (top view) note: 1. rfu1 is reserved for a12 2. rfu2 is reserved for ba2 3. vss thermal balls are optional table 1: pin description ck, /ck differential clock input ba 0 , ba 1 bank select address cke clock enable a 0 ~ a 11 address input /cs chip select dq0 ~ dq31 data input/output /ras row address strobe v dd power /cas column address strobe v ss ground /we write enable v ddq power for dq?s dqs data strobe v ssq ground for dq?s dm data mask mcl nc rfu reserved for future use dqs0 dm0 vssq dq3 dq2 dq0 dq31 dq29 dq28 vssq dm3 dqs3 vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal dq4 vddq nc vddq dq1 vddq vddq dq30 vddq nc vddq dq27 dq6 dq5 vssq vssq vssq vdd vdd vssq vssq vssq dq26 dq25 dq7 vddq vdd vss vssq vss vss vssq vss vdd vddq dq24 dq17 dq16 vddq vssq dq19 dq18 vddq vssq dqs2 dm2 nc vssq dq21 dq20 vddq vssq vssq vddq dq15 dq14 vssq vddq dq13 dq12 vssq nc dm1 dqs1 vssq vddq dq11 dq10 dq22 dq23 vddq vssq vss vss vss vss vssq vddq dq9 dq8 /cas /we vdd vss a10 vdd vdd rfu1 vss vdd nc nc /ras nc nc ba1 a2 a11 a9 a5 rfu2 ck /ck mcl /cs nc ba0 a0 a1 a3 a4 a6 a7 a8/ap cke vref 12 34567 89 101112 a b c d e f g h j k l m dqs0 dm0 vssq dq3 dq2 dq0 dq31 dq29 dq28 vssq dm3 dqs3 vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal dq4 vddq nc vddq dq1 vddq vddq dq30 vddq nc vddq dq27 dq6 dq5 vssq vssq vssq vdd vdd vssq vssq vssq dq26 dq25 dq7 vddq vdd vss vssq vss vss vssq vss vdd vddq dq24 dq17 dq16 vddq vssq dq19 dq18 vddq vssq dqs2 dm2 nc vssq dq21 dq20 vddq vssq vssq vddq dq15 dq14 vssq vddq dq13 dq12 vssq nc dm1 dqs1 vssq vddq dq11 dq10 dq22 dq23 vddq vssq vss vss vss vss vssq vddq dq9 dq8 /cas /we vdd vss a10 vdd vdd rfu1 vss vdd nc nc /ras nc nc ba1 a2 a11 a9 a5 rfu2 ck /ck mcl /cs nc ba0 a0 a1 a3 a4 a6 a7 a8/ap cke vref 12 34567 89 101112 a b c d e f g h j k l m doc # 14-02-045 rev a ecn 01-1118 3 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information # : the timing reference point for the different ial clocking is the cross point of ck and /ck. for any applications using the si ngle ended clocking, apply vref to /ck pin. table 2: input/output functional description symbol type function ck, /ck # input the differential system clock inputs. all of the input are sampled on the risi ng edge of the clock except dq?s and dm?s that are sampled on both edges of the dqs. cke input cke high activates and cke low deactivates the internal clock,input buff- ers and output drivers. by deactivating the clock, cke low indicates the power down mode or self refresh mode. /cs input /cs enables(registered low) and disables(registered high) the command decoder. when /cs is registered high,new commands are ignored but previous operations are continued. /ras input latches row addresses on the positive going edge of the ck with /ras low. enables row access & precharge. /cas input latches column addresses on the posit ive going edge of the ck with / cas low. enables column access. /we input enables write operation and row precharge. latches data in starting from / cas, /we active. dqs 0 ~ dqs 3 input, output data inputs and outputs are syn chronized with both edge of dqs. dqs0 for dq0~dq7, dqs1 for dq8~dq15, dqs2 for dq16~dq23, dqs3 for dq24~dq31 dm 0 ~ dm 3 input data-in mask. data-in is masked by dm latency=0 when dm is high in burst write. dm0 for dq0 ~ dq7, dm1 for dq8 ~ dq15, dm2 for dq16 ~ dq23, dm3 for dq24 ~ dq31. dq 0 ~ dq 31 input, output data inputs and outputs are multiplexed on the same pins. ba 0 ~ ba 1 input select which bank is to be active. a 0 ~ a 11 input row,column addresses are multiplexed on the same pin. row address : ra0 ~ ra11, column address : ca0 ~ ca7. column address ca8 is used for auto precharge. v dd , v ss power supply power and ground for the input buffers and core logic. v ddq , v ssq power supply isolated power supply and ground for the output buffers to provide improved noise immunity. v ref power supply reference voltage for inputs, used for sstl interface. nc/rfu no connection/ reserved for future use this pin is recommend to be left ?no connection? on the device. mcl must connect low not internally connected doc # 14-02-045 rev a ecn 01-1118 4 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information figure 2: functional block diag ram (1mbit x 32 i/o x 4 bank) dat a inp ut regis ter serial to parallel 1m x 32 1m x 32 1m x 32 1m x 32 sense amp column decoder late nc y & burs t le ngth programming register input buffer dll 2-bit prefetch output buffer row decoder column buffer refresh counter row buffer address register strobe ge n. timing register ck, /ck 64 lras lc br lc ke lras lc br lwe lcas lwc br ? ck,/ck 64 32 i/o control lwe ldmi x32 32 ldmi ck,/ck cke /cs /ras /cas /we dmi ck,/ck addr ba nk s elec t dqi doc # 14-02-045 rev a ecn 01-1118 5 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information figure 3: simpli fied state diagram idle row active self refresh auto refresh power down rea d writ e rea d a writ e a pre- charge power on mode regist er set pre pre bst act cke l cke h cke l cke h refa refs r ef s x refs r ef s x mrs p r e pr e power down ckel cke h ckel cke h writ e writ ea rea da rea d writ ea rea da rea da power applied rea d automatic sequence command se que nce writea : write with autoprecharge rea da : read w it h autoprecharge automatic sequence command se que nce writea : write with autoprecharge rea da : read w it h autoprecharge writ e writ ea doc # 14-02-045 rev a ecn 01-1118 6 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information functional description power-up sequence ddr sdrams must be powered up and initialized in a predefined manner to pr event undefined operations. 1. apply power and keep cke at low state (all other inputs may be undefined) - apply vdd before or at the same time as vddq. - apply vddq before or at the same time as vref & vtt 2. start clock and maintain stable condition for minimum 200s 3. the minimum of 200s after stable power and clock (ck,/ck), apply nop and cke to be high. 4. issue precharge command for all banks of the device. 5. issue a emrs command to enable dll *1 6. issue a mrs command to reset dll. the a dditional 200 clock cycles are required to lock the dll. *1,2 7. issue precharge command for all banks of the device. 8. issue at least 2 or more auto-refresh commands. 9. issue a mode register set command with a8 to low to initialize the mode register. *1 every ?dll enable? command resets dll. therefore sequence 6 can be skipped during power-up. instead of it, the additional 200cycl es of clock input is required to lock the dll after enabling dll. *2 sequence of 6 & 7 is regardless of the order. figure 4: power-up & initialization sequence /ck ck t rp 2c lo ck min. 2c lo ck min. t rp trfc trfc 2c lo ck min. precharge all banks emrs mrs dll reset precharge all banks 1s t auto refresh 2nd auto refresh mode register set any command 200 c lo ck min. command inputmustbe stable fo r 200us /ck ck t rp 2c lo ck min. 2c lo ck min. t rp trfc trfc 2c lo ck min. precharge all banks emrs mrs dll reset precharge all banks 1s t auto refresh 2nd auto refresh mode register set any command 200 c lo ck min. command inputmustbe stable fo r 200us doc # 14-02-045 rev a ecn 01-1118 7 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information mode register set (mrs) the mode register stores the data for controlling the various operating modes of ddr sdram. it programs /cas latency, address mode, burst length, test mode, dll rese t and various vendor specific option to make ddr sdram useful for variety of different applications. the default val ue of the mode register is not defined, therefore the mode register must be written after emrs setting for proper opera tion. the mode register is wr itten by asserting low on /cs, /ras, /cas and we (the ddr sdram should be in active m ode with cke already high prior to writing into the mode register). the state of address pins a0 ~ a11 and ba0,ba1 in the same cycl e as /cs, /ras, /cas and /we going low is written in the mode register. minimum two clock cycles ar e requested to complete the write operation in the mode register. the mode register contents can be changed usin g the same command and clock cycle requirements during operation as long as all banks are in the idle state. the mode register is divided into various fields depending on functionality. the burst length uses a0~a2, address mode uses a3, /cas latency (read latency from column address) uses a4 ~ a6. a7 is used for test mode. a8 is used for d ll for dll reset. a7, a8, ba0, and ba1 must be set to low for normal mrs operation. refer to the table for specific codes for various burst length, address modes and /cas latencies. figure 5: mrs cycle * 1 : mrs can be issued only at all banks precharge state. * 2 : minium t rp is required to issue mrs command. ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 address bus rfu 0 dll tm bt rfu /cas latency burst length mode register dll reset a 8 mode a 7 type a 3 burst type test mode dll no 0 normal 0 yes 1 test 1 sequential 0 interleave 1 mode ba 0 mrs 0 emrs 1 latency a 4 reserved 0 reserved 1 a 5 0 0 a 6 0 0 2 0 3 1 1 1 0 0 reserved 0 reserved 1 0 0 1 1 reserved 0 reserved 1 1 1 1 1 int erleave reserved 2 4 8 reserved reserved reserved reserved sequential reserved 2 4 8 reserved reserved reserved full page 0 1 0 0 0 0 0 1 1 1 0 0 0 1 0 0 1 1 0 1 1 1 1 1 burst type a 0 a 1 a 2 burst length /cas latency * rfu(reserved for future use) sho uld st ay ?0? during mrs c yc le . 0 12345678 no p precharge all banks no p no p mrs * 1 no p any command no p no p t rp * 2 t mr d =2 t ck /ck ck command 0 12345678 no p precharge all banks no p no p mrs * 1 no p any command no p no p t rp * 2 t mr d =2 t ck /ck ck command doc # 14-02-045 rev a ecn 01-1118 8 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information extended mode register set (emrs) the extended mode register stores the data for enabling or disabling dll and selectin g output driver strength. the default value of the extended mode regist er is not defined, therefor e the extended mode register must be written after power up for enabling or disabling dll. the extended mode re gister is written by asserting low on /cs, /ras, /cas, / we and high on ba0 (the ddr sdram should be in all bank precharge with cke already high prior to writing into the extended mode register). the state of address pins a0,a2~a5, a7~a11 and ba1 in the same cycle as /cs,/ras,/cas and /we going low are written in the extended mode register. a1 and a6 are used for setting driver strength to weak or matched impedance. two clock cycles are required to complete the write operation in t he extended mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state a0 is used for dll enable or disable.?high?on ba0 is used for emrs. all the other address pins except a0,a1, a6 and ba0 must be set to low for proper emrs operation. refer to the table for specific codes. figure 6: low freque ncy operation mode notes: - dll disable mode is operating mode for low operat ing frequency between 143mhz and 83mhz without dll. - this dll disable mode is useful for power saving. - all banks precharge or a bank precharge command ca n omit before entering and exiting dll disable mode. *1 : cl=2 & 3 and bl can set any burst length at dll disable mode. *2 : a read command can be applied as far as tr cd is satisfied after any bank active command. and it needs an additional 200 clock cycles fo r read operation after exiting dll disable mode. address bus ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 rfu 1 rfu extended mode register mode ba 0 mrs 0 emrs 1 ? rfu(reserved for future use) should stay ?0? during mrs cycle. dic dll dic rfu output driver impedance control a 6 60% of full drive st rength 0 30% of full drive st rength 1 dll enable a 0 enable 0 disable 1 a 1 1 1 weak matched impedance dll disable mode /ck ck t rp 2c lo ck min. 2c lo ck min. precharge all banks emrs mrs *1 cmd mrs ac tiv e read *2 200 c lo ck min. command enter dll disable mode 2c lo ck min. emrs 2c lo ck min. dll disable mode t rp precharge all banks exit dll disable mode mrs dll reset 2c lo ck min. cl=2/3 bl=free dll disable mode /ck ck t rp 2c lo ck min. 2c lo ck min. precharge all banks emrs mrs *1 cmd mrs ac tiv e read *2 200 c lo ck min. command enter dll disable mode 2c lo ck min. emrs 2c lo ck min. dll disable mode t rp precharge all banks exit dll disable mode mrs dll reset 2c lo ck min. cl=2/3 bl=free doc # 14-02-045 rev a ecn 01-1118 9 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information burst mode operation burst mode operation is used to prov ide a constant flow of data to memory location (write cycle) , or from memory location (read cycle). there are two para meters that define how the burst mode operates. these parameters including burst sequence and burst length are pr ogrammable and determined by address a0 ~ a3 during the mode register set command. the burst type is used to define the sequence in which the burst data will be delivered or stored to the ddr sdram. two types of burst sequences are supported, sequ ential and interleaved. see the below table. the burst length controls the number of bits that will be output after a read command, or the number of bits to be input after a write command. the burst length can be programmed to have values of 2,4,8 or full page. for the full page operation, the starting address must be an even numb er and the burst stop at the end of burst. bank activation command the bank activation command is issued by holding /c as and /we high with /cs and /ras low at the rising edge of the clock. the ddr sdram has four independent banks, so two bank select addresses(ba0, ba1) are supported. the bank activation command must be applied before any read or write operation is executed.the delay from the bank activation command to the first read or write comma nd must meet or exceed the minimum of /ras to /cas delay time (trcdr/trcdw min). once a bank has been activated, it must be prec harged before another bank activation command can be applied to the same bank. the minimum time interval between interleaved bank activation commands(bank a to b and vice versa) is the bank to bank delay time (trrd min). figure 7: bank activation co mmand cycle (/cas latency = 3) table 3: burst le ngth and sequence burst length starting address (a 2 , a 1 , a 0 ) sequential mode interleave mode 2 xx0 0-1 0-1 xx1 1-0 1-0 4 x00 0-1-2-3 0-1-2-3 x01 1-2-3-0 1-0-3-2 x10 2-3-0-1 2-3-0-1 x11 3-0-1-2 3-2-1-0 8 000 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 001 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 010 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 011 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 100 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 101 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 110 6-7-0-1-2-3-4-5 6-7-4-5-0-1-2-3 111 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (256) n = a0 - a7, a0 = 0 c n, cn+1, cn+2, ..., cn-1 not supported 01 2 nn+1n+2 bank a row a ddr. bank a col. addr. bank a row a ddr. bank b row a ddr. bank a activate nop nop rea d a with auto bank a activate nop bank b activate /ras-/cas delay time (trcdr for read) /ras-/ras delay time (trrd) precharge row cycle t ime (t rc ) :don?tcare /ck ck address command 01 2 nn+1n+2 bank a row a ddr. bank a col. addr. bank a row a ddr. bank b row a ddr. bank a activate nop nop rea d a with auto bank a activate nop bank b activate /ras-/cas delay time (trcdr for read) /ras-/ras delay time (trrd) precharge row cycle t ime (t rc ) :don?tcare /ck ck address command doc # 14-02-045 rev a ecn 01-1118 10 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information burst read operation burst read operation in ddr sdram is in the same manner as the current sdram such that the burst read command is issued by asserting /cs and /cas low while hold ing /ras and /we high at the rising edge of the clock after trcd from the bank activation. the address inputs (a0~a7) determine the starting address for the burst. the mode register sets type of burst (sequential or interleave) and burst length(2,4,8, full page). the first output data is available after the /cas latency from the read command, and the consecutive data are presented on the falling and rising edge of data strobe adopted by ddr sdram until the burst length is completed. figure 8: burst read (burst length = 4, /cas latency = 3) burst write operation the burst write command is issued by having /cs, /cas and /we low while holding /ras high at the rising edge of the clock. the address inputs determine the starting column a ddress. there is no real wr ite latency required for burst write cycle. the first data for bu rst write cycle must be appli ed at the first rising edge of the data str obe enabled after tdqss from the rising edge of the clock that the write command is issued.the re maining data inputs must be supplied on each subsequent falling and rising edge of data strobe unti l the burst length is completed. when the burst has been finished, any additional data supplied to the dq pins will be ignored. figure 9: burst writ e (burst length = 4) 012 nop /ck ck command 345 67 8 nop nop nop nop nop nop nop rea d t rpre t rpst dqs do ut 0 do ut 1 do ut 2 do ut 3 dq?s /cas latency = 3 012 nop /ck ck command 345 67 8 nop nop nop nop nop nop nop rea d t rpre t rpst dqs do ut 0 do ut 1 do ut 2 do ut 3 dq?s /cas latency = 3 012 writea /ck ck command 345 67 8 nop writeb nop nop nop nop nop nop t dqssmax t wpst dqs din a 2 din a 3 din b 0 din b 1 dq?s din b 2 din b 3 din a 0 din a 1 t wpreh t wpres 012 writea /ck ck command 345 67 8 nop writeb nop nop nop nop nop nop t dqssmax t wpst dqs din a 2 din a 3 din b 0 din b 1 dq?s din b 2 din b 3 din a 0 din a 1 t wpreh t wpres doc # 14-02-045 rev a ecn 01-1118 11 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information burst interruption read interrupted by read burst read can be interrupted before completion of th e burst by new read command of any bank. when the previous burst is interrupted, the remaining address are ov erridden by the new address with the full burst length. the data from the previous read command continues to appear on the outputs until the /cas latency from the interrupting read command is satisfied. read to read interval is minimum 1 tck. figure 10: burst interrupted by read (burst length = 4, /cas latency = 3) read interrupted by burst stop & write to interrupt burst read with a write command, burst st op command must be asserted to avoid data contention on the i/o bus by placing the dq ?s(output drivers) in a high impedance st ate at least one clock cycle before the write command is initiated. once the burs t stop command has been issued, the minimum delay to a write command is cl(ru). [cl is /cas latency and ru means round up to the nearest integer.] figure 11: burst interrupted by burst stop & write ( burst length = 4, /cas latency = 3 ) 012 rea d b /ck ck command 345 67 8 nop nop nop nop nop nop nop rea d a dqs do uta0 do uta1 do utb 0 do utb 1 dqs do utb 2 do utb 3 /cas latency = 3 012 rea d b /ck ck command 345 67 8 nop nop nop nop nop nop nop rea d a dqs do uta0 do uta1 do utb 0 do utb 1 dqs do utb 2 do utb 3 /cas latency = 3 012 burst stop /ck ck command 34567 8 nop nop nop write nop nop rea d dqs do ut0 do ut1 din 0 din 1 dq?s din 2 din 3 /cas latency = 3 t rpre preamble t wpreh t dqss t wpres 012 burst stop /ck ck command 34567 8 nop nop nop write nop nop rea d dqs do ut0 do ut1 din 0 din 1 dq?s din 2 din 3 /cas latency = 3 t rpre preamble t wpreh t dqss t wpres doc # 14-02-045 rev a ecn 01-1118 12 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information read interrupted by precharge burst read can be interrupted by precharge of the same bank. the minimum 1 clock cycle is required for the read precharge interval. precharge command to output disable latency is equivalent to the /cas latency. figure 12: burst interrupted by precharge (burst length = 8, /cas latency = 3) write interrupted by write burst write can be interrupted by the new write command be fore completion of the previous burst write, with the only restriction being that the interval that separates the co mmands must be at least one clock cycle. when the previous burst is interrupted, the remaining addresses are overri dden by the new addresses and data will be written into the device until the programmed burst length is satisfied. figure 13: write interrupted by write (burst length = 4) 012 precharge /ck ck command 345 67 8 nop nop nop nop nop nop rea d dqs dq?s do ut 0 do ut 1 do ut 2 do ut 3 do ut 4 do ut 5 /cas latency = 3 1t ck do ut 6 do ut 7 interrupted by precharge t rpre t rpst nop 012 writea /ck ck command 345 67 8 writeb nop nop nop nop nop nop nop dqs dq?s din a 0 din a 1 din b 0 din b 1 din b 2 din b 3 /cas latency = 3 1t ck t wpreh t wpres doc # 14-02-045 rev a ecn 01-1118 13 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information write interrupted by read & dm a burst write can be interrupted by a read command of any bank. the dq?s must be in the high impedance state at least one clock cycle before the interrupting read data appe ar on the outputs to avoid data contention. when the read command is registered, any residual data from the burst wr ite cycle must be masked by dm . the delay from the last data to read command (twtr) is required to avoid the data contention dram inside. data that are presented on the dq pins before the read command is in itiated will actually be written to the memory. read command interrupting write can not be issued at the next clock edge of the write command. figure 14: write interrupted by read & dm (burst length = 8) write /ck ck command nop nop nop nop rea d nop nop 012345678 dqs dq?s din 0 din 1 din 2 din 3 din 4 din 5 /cas late nc y=3 t dqssmax t wpres t wtr din 6 din 7 dqs dq?s din 0 din 1 din 2 din 4 din 5 din 6 din 7 dm din 3 /cas late nc y=3 do ut0 do ut1 t dqssmin t wpres dm t wtr do ut0 do ut1 nop write /ck ck command nop nop nop nop rea d nop nop 012345678 012345678 012345678 012345678 dqs dq?s din 0 din 1 din 2 din 3 din 4 din 5 /cas late nc y=3 t dqssmax t wpres t wtr din 6 din 7 dqs dq?s din 0 din 1 din 2 din 4 din 5 din 6 din 7 dm din 3 /cas late nc y=3 do ut0 do ut1 t dqssmin t wpres dm t wtr do ut0 do ut1 nop doc # 14-02-045 rev a ecn 01-1118 14 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information write interrupted by precharge & dm a burst write can be interrupted by a precharge of the same bank before co mpletion of the previous burst. a write recovery time (twr) is required from the last data to precharge command . when precharge command is asserted, any residual data from the burst write cycle must be masked by dm. figure 15: write interrup ted by precharge & dm 012 writea /ck ck command 345678 nop nop nop nop precharge write b nop nop dqs dq?s din a 0 din a 1 din a 2 din a 3 din a 4 din a 5 max t dq ss t dqssmax t wpreh t wpres t wpreh t dqssmax t wpres t wr din a 6 din a 7 din a 0 din a 1 dm dqs dq?s din a 0 din a 1 din a 2 din a 4 din a 5 min t dqs s t dqssmin t wpreh t wpres t wpreh t dqssmin t wpres din a 6 din a 7 din b 0 din b 1 dm t wr din b 2 din a 3 012 writea /ck ck command 345678 nop nop nop nop precharge write b nop nop dqs dq?s din a 0 din a 1 din a 2 din a 3 din a 4 din a 5 max t dq ss t dqssmax t wpreh t wpres t wpreh t dqssmax t wpres t wr din a 6 din a 7 din a 0 din a 1 dm dqs dq?s din a 0 din a 1 din a 2 din a 4 din a 5 min t dqs s t dqssmin t wpreh t wpres t wpreh t dqssmin t wpres din a 6 din a 7 din b 0 din b 1 dm t wr din b 2 din a 3 doc # 14-02-045 rev a ecn 01-1118 15 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information burst stop command the burst stop command is initiated by having /ras and /c as high with /cs and /we low at the rising edge of the clock only. the burst stop command has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. when the burst stop command is issued during a burst read cycle, both the data and dq s(data strobe) go to a high impedance state after a dela y which is equal to the /cas latency set in the mode register. the burst stop command, however, is not supported during a write burst operation. figure 16: burst stop command (burst length = 4, /cas latency = 3) dm function the ddr sdram has a data mask func tion that can be used in conjuncti on with data write cycle only, not read cycle. when the data mask is activated (dm high) during writ e operation, the write data is masked immediately (dm to data-mask latency is zero). dm must be issued at the rising edge or the falling e dge of data strobe instead of a clock edge. figure 17: dm functi on (burst length = 8) 012 burst st op /ck ck command 345 67 8 nop nop nop nop nop nop nop rea d dqs dq?s do ut 0 do ut 1 /cas latency = 3 1t ck the burst ends after a delay equal to the /cas latency 012 burst st op /ck ck command 345 67 8 nop nop nop nop nop nop nop rea d dqs dq?s do ut 0 do ut 1 /cas latency = 3 1t ck the burst ends after a delay equal to the /cas latency 012 nop /ck ck command 345 67 8 nop nop nop nop nop nop nop write dqs dq?s din 0 t dqss t wpreh t wpres din 1 din 2 din 3 din 4 din 5 din 6 din 7 masked by dm=h dm dm 012 nop /ck ck command 345 67 8 nop nop nop nop nop nop nop write dqs dq?s din 0 t dqss t wpreh t wpres din 1 din 2 din 3 din 4 din 5 din 6 din 7 masked by dm=h dm 012 nop /ck ck command 345 67 8 nop nop nop nop nop nop nop write dqs dq?s din 0 t dqss t wpreh t wpres din 1 din 2 din 3 din 4 din 5 din 6 din 7 masked by dm=h dm dm doc # 14-02-045 rev a ecn 01-1118 16 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information auto-precharge operation the auto precharge command can be issued by having column address a8 high when a read or a write command is asserted into the ddr sdram. if a8 is low when read or write command is issued, normal read or write burst operation is asserted and the bank remains active after the completion of the burst sequence. when the auto precharge command is activated, the ac tive bank automatically begins to prec harge at the earliest possible moment during read or write cycle after tras (min) is satisfied. read with auto precharge if a read with auto-precharge command is initiated, th e ddr sdram automatically starts the precharge operation on 2 clock previous to the end of burst from a read with auto-precharge command when tras (min) is satisfied. if not, the start point of precharge operation will be delayed until tr as (min) is satisfied. the bank started the precharge operation once cannot be reactivated and the new comma nd can not be asserted until the precharge time (trp) is satisfied. figure 18: read with auto precharge (burst length = 4, /cas latency = 3) when the read with auto precharge command is issued, new command can be asserted at t5, t6 and t7 respectively as follows. ap = auto precharge asserted command for same bank for different bank t5 t6 t7 t5 t6 t7 read read (no ap) read (no ap) illegal legal legal legal read + ap read + ap read + ap illegal legal legal legal active illegal illegal illegal legal legal legal precharge legal legal illegal legal legal legal 012 nop /ck ck command 345 67 8 nop rea d a auto prec har ge nop nop nop nop nop bank a active dqs dq?s do uta0 do uta1 /cas latency = 3 * bank can be reactiv ated at completion of t rp trc dr ( min ) tras (min ) t rp do uta2 do uta3 auto-precharge start point t rc(min) 012 nop /ck ck command 345 67 8 nop rea d a auto prec har ge nop nop nop nop nop bank a active dqs dq?s do uta0 do uta1 /cas latency = 3 * bank can be reactiv ated at completion of t rp trc dr ( min ) tras (min ) t rp do uta2 do uta3 auto-precharge start point t rc(min) doc # 14-02-045 rev a ecn 01-1118 17 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information write with auto precharge if a8 is high when write command is issued, the write with auto-precharge function is performed. any new command to the same bank should not be issued until the internal pr echarge is completed. the internal precharge begins after keeping twr (min). figure 19: write with auto precharge (burst length = 4, /cas latency = 3) ap = auto precharge dm : refer to ?write interrupted by read & dm? asserted command for same bank for different bank 3 4 5 6 7 8 3 4 5 6 7 write write no ap write no ap write no ap illegal illegal illegal legal legal legal legal legal write + ap write + ap write + ap write + ap illegal illegal illegal legal legal legal legal legal read illegal read no ap + dm read no ap + dm read no ap read no ap illegal illegal illegal illegal legal legal read + ap illegal read + ap + dm read + ap + dm read + ap read + ap illegal illegal illegal illegal legal legal active illegal illegal illegal illegal illegal illegal legal legal legal legal legal precharge illegal illegal illegal illegal illegal illegal legal legal legal legal legal 012 /ck ck command 345678 nop nop nop nop nop nop bank a active dqs dq?s din a 0 din a 1 /cas latency = 3 rp t din a 2 din a 3 internal precharge starts t rp 012 write a auto prec har ge /ck ck command 345678 nop nop nop nop nop nop nop bank a active dqs dq?s din a 0 din a 1 /cas latency = 3 * bank can be reactivated at completion of t wp reh t wr din a 2 din a 3 internal precharge starts t wp res t doc # 14-02-045 rev a ecn 01-1118 18 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information precharge command the precharge command is issued when /cs, /ras, and /w e are low and /cas is high at the rising edge of the clock, ck. the precharge command can be used to precharge each bank respectively or all banks simultaneously. the bank select addresses(ba0, ba1) are used to define which bank is precharged when the command is initiated. for write cycle, twr (min). must be satisfied from the start of the last burst write cycle until t he precharge command can be issued. after trp from the precharge, an acti ve command to the same bank can be initiated. auto refresh an auto refresh command is issued by having /cs, /ras and /cas held low with cke and /we high at the rising edge of the clock, ck. all banks must be precharged and idle for a trp (min) before the auto refresh command is applied. the refresh addressing is generated by the internal refresh address counter. this makes the address bits ?don?t care? during an auto refresh command. when the re fresh cycle has completed, all banks will be in the idle state. a delay between the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the trfc (min). figure 20: auto refresh table 4: bank selection for pr echarge by bank address bits a8/ap ba1 ba0 precharge 0 0 0 bank a only 0 0 1 bank b only 010bank c only 011bank d only 1 x x all banks 012 /ck ck command 345 67 8 pre trfc t rp 91011 auto refresh cmd cke=high 012 /ck ck command 345 67 8 pre trfc t rp 91011 auto refresh cmd cke=high all banks doc # 14-02-045 rev a ecn 01-1118 19 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information self refresh a self refresh command is defined by having /cs, /r as, /cas and cke low with /we high at the rising edge of the clock (ck). once the self refresh command is initiated, cke must be held low to keep the device in self refresh mode. during the self refresh operation, all inputs except cke are ignored. the clock is internally disabled during self refresh operation to reduce power consumption. the self refresh is exited by supplying stable clock input before returning cke high, asserting deselect or nop command and then asse rting cke high for longer than txsr for locking of dll. figure 21: self refresh *1 exit self refresh to bank active command, a write command c an be applied as far as trcd is sa tisfied after any bank active c om- mand. *2 exit self refresh to read command. power down mode the power down is entered when cke low, and exited wh en cke high. once the power down mode is initiated, all of the receiver circuits except ck and cke are gated off to reduce power consumption. all banks should be in idle state prior to entering the precharge power down mode and c ke should be set high at least 1tck+tis prior to row active command. during power down mode, refresh oper ations cannot be performed, therefore the device cannot remain in power down mode longer than the refresh period (t ref) of the device. figure 22: power down mode /ck ck command self refresh t xsa *1 t xsr *2 cke active read t is /ck ck command self refresh t xsa *1 t xsr *2 cke active read t is self refresh pre all banks /ck ck command 012345 67 8 91011 cke 12 13 prech arge prech arge pow er dow n ent ry prech arge pow er dow n exit active pow er dow n ent ry active active pow er dow n exit read nop nop t is t is t is t is t pdex /ck ck command 012345 67 8 91011 cke 12 13 prech arge prech arge pow er dow n ent ry prech arge pow er dow n exit active pow er dow n ent ry active active pow er dow n exit read nop nop t is t is t is t is t pdex doc # 14-02-045 rev a ecn 01-1118 20 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information note : permanent device damage may occur if absolute maximum rating are exceeded. functional operation should be re stricted to recommended operating condition. exposure to higher than recommended voltage for ext ended periods of time could affect device reliability. note : 1. vdd / vddq = 2.5v 5% / 2.5v 5% 2. vref is expected to equal 0.50* vddq of the transmitting device and to track variations in the dc level of the same. pea k to peak noise on the vref may not exceed 2% of the dc value. thus, from 0.50* vddq, vref is allowed 25mv for dc error and an additional 25mv for ac noise. 3. vtt of the transmitting device mu st track vref of the receiving device. 4. vih(max.) = vddq +1.5v for a pulse and it which can not be greater than 1/3 of the cycle rate. 5. vil(mim.) =-1.5v for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. for any pin under test input of 0v vin vdd is acceptable. for all other pins that are not under test vin = 0v. 7. voh (output logic high voltage) min = vtt (min) + 0.76 8. vol (output logic low voltage) max = vtt (max) - 0.76 9. dqs are disabled; 0v vout vddq table 5: absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss vin, vout -0.5~3.6 v voltage on vdd supply relative to vss vdd -1.0~3.6 v voltage on vddq supply relative to vss vddq -0.5~3.6 v storage temperature tstg -55~150 c power dissipation pd 2.0 w short circuit current ios 50 ma table 6: power & dc operating condi tion (sstl_2 in/out) recommended operating conditions (voltage referenced to vss, ta = 0 to 70c parameter symbol min typ max unit note device supply voltage v dd 2.375 2.50 2.625 v 1 output supply voltage v ddq 2.375 2.50 2.625 v 1 reference voltage v ref 0.49*v ddq -- 0.51*v ddq v2 termination voltage v tt v ref -0.04 v ref v ref +0.04 v3 input logic high voltage v ih v ref +0.15 -- v ddq +0.30 v4 input logic low voltage v il -0.30 -- v ref -0.15 v5 output logic high current i oh -15.2 -- -- ma 7 output logic low current i ol 15.2 -- -- ma 8 input leakage current i il -5 -- 5 ua 6 output leakage current i ol -5 -- 5 ua 9 doc # 14-02-045 rev a ecn 01-1118 21 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information note: 1. measured with outputs open. 2. refresh period is 32ms. note : 1. vid is the magnitude of the difference between the input level on ck and the input level on /ck 2. the value of vix is expected to equal 0.5* vddq of th e transmitting device and must track va riation in the dc level of t he same table 7: dc characteristic recommended operating conditions (voltage reference to vss=0v, vdd/vddq=2.5v5%/2.5v5%, ta= 0 to 70c) parameter symbol test condition all unit note operating current (one bank active) icc1 burst length=2, trc trc(min) iol=0ma, tck=tck(min) 160 ma 1 precharge standby current in power down mode icc2p cke vil(max), tck=tck(min) 15 ma precharge standby current in non power down mode icc2n cke vih(min), /cs vih(min) tck=tck(min) 40 ma active standby cur- rent in power down mode icc3p cke vil(max), tck=tck(min) 17 ma active standby cur- rent in non power down mode icc3n cke vih(min), /cs vih(min) tck=tck(min) 70 ma operating current (burst mode) icc4 iol=0ma, tck=tck(min), page burst, all banks activated 420 ma refresh current icc5 trc trfc(min) 200 ma 2 self refresh current icc6 cke 0.2v 6 ma operating current (4bank interleaving) icc7 burst length=4, trc trc(min) iol=0ma, tck=tck(min) 560 ma table 8: ac input operating condit ions recommended operating conditions (voltage reference to vss=0v, vdd/vddq=2.5v5%/2.5v5%, ta= 0 to 70c) parameter symbol min typ max unit note input high (logic1) voltage : dq vih v ref +0.35 -- -- v input low (logic0) voltage: dq vil -- -- v ref -0.35 v clock input differential voltage; ck and /ck vid 0.7 -- v ddq +0.6 v1 clock input crossing point voltage; ck and /ck vix 0.5*v ddq -0.2 -- 0.5*v ddq +0.2 v2 doc # 14-02-045 rev a ecn 01-1118 22 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information figure 23: output load circuit note : 1. vdd and vddq pins are separated from each other. all vdd pins are connected internally on-chip. all vddq pins are connected internally on-chip. 2. vss and vssq pins are separated each other. all vss pins are connected internally on- chip. all vssq pins are c onnected internally on-chip. table 9: ac operating test condi tions (v dd = 2.5v0.125v, ta=0 to 70c) parameter value unit note input reference voltage for ck (for signal ended) 0.50*v ddq v ck and /ck signal maximum peak swing 1.5 v ck signal minimum slew rate 1.0 v/ns input levels(vih/vil) v ref +0.35/v ref -0.35 v input timing measurement reference level v ref v output timing measurement reference level vtt v output load condition see figure 23 table 10: capacitance (v dd = 2.5v, ta = 25c, f = 1mhz) parameter symbol min max unit input capacitance (ck, /ck) cin1 2.0 3.0 pf input capacitance (a0~a11, ba0~ba1) cin2 2.0 3.0 pf input capacitance (cke, /cs, /ras, /cas, /we) cin3 2.0 3.0 pf data & dqs input/output capaci tance (dq0~dq31) cout 4.0 5.0 pf input capacitance (dm0~dm3) cin4 4.0 5.0 pf table 11: decoupling capacitance guide line (recommended decoupling capacitance added to power line at board) parameter symbol value unit decoupling capacitance between vdd and vss cdc1 0.1+0.01 f decoupling cpaacitance between vddq and vssq cdc2 0.1+0.01 f o n o output z0=50 ? c load =20pf v ref =0.5*v ddq r t =50 ? vtt=0.5*v ddq o n o output z0=50 ? c load =20pf v ref =0.5*v ddq r t =50 ? vtt=0.5*v ddq doc # 14-02-045 rev a ecn 01-1118 23 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information . note 1: -. the jedec ddr specification currently defines the output data valid window (tdv) as the period when the data strobe and all data associated with that data strobe are coincidentally valid. -. the previously used definition of tdv( =0.35tdk) artificially penalizes system timing budgets by assuming the worst case out put valid window even then the clock duty cycle applied to the device is better than 45/55% -. a new ac timing term, tqh which stands for data output hold time from dqs is defined to account for clock duty cycle variati on and replaces tdv - tqhmin = thp-x where . thp=minimum half clock period for any gi ven cycle and is defined by clock high or clock low time (tch, tcl). .x=a frequency dependent timi ng allowance account for tdqsqmax note 2 -. for low frequency operation without dll (143mhz~83mhz) in cl2/3, need set dll disable mode for power saving. -. ac parameters for dll disable mode : same as ?-50? ac parameters except tck. note 3 -. under set dll disable mode by emrs, -. the tdqsck can be 0.0ns in 100mhz operation. -. the tdqsck can be +3.0ns in 143mhz operation. -. the tdqsck can be -2.0ns in 83mhz operation. table 12: ac characteristics parameter symbol -5g -5 -6 unit note min max min max min max ck cycle time cl=3 5.0 12 5.0 12 6.0 12 ns 2,3 cl=2 9.012--------ns2,3 ck high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck ck low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs out access time from ck t dqsck -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns output access time from ck t ac -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns data strobe edge to dout edge t dqsq -- 0.45 -- 0.45 -- 0.45 ns 1 read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in t dqss 0.8 1.2 0.8 1.2 0.8 1.2 tck dqs-in setup time t wpres 0--0--0--ns dqs-in hold time t wpreh 0.3 -- 0.3 -- 0.3 -- tck dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs-in high level width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs-in low level width t dqsl 0.4 0.6 0.4 0.6 0.4 0.6 tck address and control input setup t is 1.0 -- 1.0 -- 1.0 -- ns address and control input hold t ih 1.0 -- 1.0 -- 1.0 -- ns dq and dm setup time to dqs t ds 0.45 -- 0.45 -- 0.45 -- ns dq and dm hold time to dqs t dh 0.45 -- 0.45 -- 0.45 -- ns clock half period t hp t cl- min or t ch- min -- t cl- min or t ch- min -- t cl- min or t ch- min -- ns 1 data output hold time from dqs t qh t hp -0.45 -- t hp -0.45 -- t hp -0.45 -- ns 1 doc # 14-02-045 rev a ecn 01-1118 24 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information note 1 1. for normal write operation, even numbers of din are to be written inside dram -. ac parameters for dll disable mode(143mhz ~ 83mhz, cl2/3 only) table 13: ac characteristics (cont) parameter symbol -5g -5 -6 unit note min max min max min max row cycle time t rc 60 -- 60 -- 60 -- ns refresh cycle time t rfc 70 -- 70 -- 70 -- ns row active time t ras 40 100k 40 100k 40 100k ns /ras to /cas delay to read t rcdr 18 -- 18 -- 18 -- ns /ras to /cas delay to write t rcdw 10 -- 10 -- 10 -- ns row precharge time t rp 18 -- 18 -- 18 -- ns row active to row active t rrd 2--2--2--tck last data in to row precharge t wr 2--2--2--tck1 last data in to row precharge (auto precharge) t wr_a 2--2--2--tck1 internal write in to read t wtr 2--2--2--tck1 col. address to col. address t ccd 1--1--1--tck mode reigister set cycle time t mrd 2--2--2--tck auto precharge write recovery + precharge t dal 6--6--6--tck exit self refresh to active command t xsa 75 -- 75 -- 75 -- ns exit self refresh to read command t xsr 200 -- 200 -- 200 -- tck power down exit time t pdex 1tck +tis -- 1tck +tis -- 1tck +tis -- ns refresh interval time t ref 7.8 -- 7.8 -- 7.8 -- us doc # 14-02-045 rev a ecn 01-1118 25 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information note 1. op code : operand code. a0 ~ a11 & ba0 ~ ba1 : program keys. (@emrs/mrs) 2. emrs/mrs can be issued only at all banks precharge state. a new command can be issued after 2 clock cycle of emrs/mr s 3. auto refresh function are as same as cbr refresh of dram. the automatic precharge without row precharge command is meant by ?auto?. auto/self refresh can be issued only at all banks precharge state. 4. ba0 ~ ba1 : bank select addresses. if both ba0 and ba1 are ?low? at read, write, row active and precharge, bank a is selected. if ba0 is ?high? and ba1 is ?low? at read, write, row active and precharge, bank b is selected. if ba0 is ?low? and ba1 is ?high? at read, write, row active and precharge, bank c is selected. if both ba0 and ba1 are ?high? at read, write, row active and precharge, bank d is selected. 5. if a8/ap is ?high? at row precharge ,ba0 and ba1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command cannot be issued. another bank read/write command can be issued after the end of burst. new row active of the as sociated bank can be issued at trp after the end of burst. 7. burst stop command is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and data-in are masked at the both edges(write dm latency is 0). table 14: simplified truth table command cken-1 cken /cs /ras /cas /we dm ba 0,1 a8/ap a11~a9, a7~a0 note register extended mode register hxllllx op code 1,2 mode register set hxllllx op code refresh auto refresh h h ll lhx x 3 self refresh entry l 3 exit l h lh hh xx 3 hx x x 3 bank active & row address h x l l h h x v row address read & col addr. auto precharge disable hxlhlhxv l column address 4 auto precharge enable h4 write & col addr. auto precharge disable hxlhllxv l column address 4 auto precharge enable h4,6 burst stop h x l h h l x x 7 pre- charge bank selection hxllhlx vl x all banks x h 5 active power down entry h l hx x x x x lv vv exit l h x x x x x precharge power down mode entry h l hx x x x x lh hh exit l h hx x x x lh hh dm h x v x 8 no operation command h x hx x x xx lh hh doc # 14-02-045 rev a ecn 01-1118 26 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information table 15: function truth table current state /cs /ras /cas /we address command action idle h x x x x desel nop lh hhx nop nop lh hlx term nop lh lx b a0 , ca, a 8 read/write illegal*2 l l h h ba, ra act bank active, latch ra l l h l ba, a8 pre/prea nop*4 l l l h x refa auto-refresh*5 ll ll op-code, mode -add mrs mode register set*5 row active h x x x x desel nop lh hhx nop nop lh hlx term nop l h l h ba, ca, a8 read/reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a8 write/writea begin write, latch ca, determine auto-precharge l l h h ba, ra act illegal*2 l l h l ba, a8 pre/prea precharge/precharge all l l l h x refa illegal ll ll op-code, mode-add mrs illegal read h x x x x desel nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l x term terminate burst l h l h ba, ca, a8 read/reada terminate burst, latch ca, begin new read, determine auto-precharge*3 l h l l ba, ca, a8 write/writea illegal l l h h ba, ra act illegal*2 l l h l ba, a8 pre/prea terminate burst, precharge l l l h x refa illegal ll ll op-code, mode-add mrs illegal write h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l x term illegal l h l h ba, ca, a8 read/reada illegal l h l l ba, ca, a8 write/writea terminate burst, latch ca, begin new write, determine precharge*3 l l h h ba, ra act illegal*2 l l h l ba, a8 pre/prea terminate burst with dm-high precharge l l l h x refa illegal ll ll op-code, mode-add mrs illegal doc # 14-02-045 rev a ecn 01-1118 27 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information read with auto precharge h x x x x desel nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l x term illegal l h l x ba, ra, a8 read/write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a8 pre/prea illegal*2 l l l h x refa illegal ll ll op-code, mode-add mrs illegal write with auto precharge h x x x x desel nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l x term illegal l h l x ba, ca, a8 read/write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a8 pre/prea illegal*2 l l l h x refa illegal ll ll op-code, mode-add mrs illegal pre- charging h x x x x desel nop(idle after trp) l h h h x nop nop(idle after trp) lh hlx term nop l h l x ba, ca, a8 read/write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a8 pre/prea illegal*2 l l l h x refa illegal ll ll op-code, mode-add mrs illegal row activating h x x x x desel nop(row active after trcd) l h h h x nop nop(row active after trcd) lh hlx term nop l h l x ba, ca, a8 read/write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a8 pre/prea illegal*2 l l l h x refa illegal ll ll op-code, mode-add mrs illegal write recover- ing h x x x x desel nop lh hhx nop nop lh hlx term nop l h l h ba, ca, a8 read illegal*2 l h l l ba, ca, a8 write/writea new write, determine ap. l l h h ba, ra act illegal*2 l l l h ba, a8 pre/prea illegal*2 l l l l x refa illegal ll ll op-code, mode-add mrs illegal table 15: function truth table current state /cs /ras /cas /we address command action doc # 14-02-045 rev a ecn 01-1118 28 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information abbreviations : h=high level, l=low level, v=valid, x=don?t care ba=bank address, ra=row address, ca=column address, nop=no operation note : 1. all entries assume that cke was high durin g the preceding clock cycle a nd the current clock cycle. 2. illegal to bank in specified state ; function may be le gal in the bank indicated by ba, depending on the state of that b ank. 3. must satisfy bus contention, bus turn around, write recovery requirements. 4. nop to bank precharging or in idle state, may precharge bank indicated by ba. 5. illegal if any bank is not idle. 6. same bank?s previous auto precharge will not be performed. but if bank is different, previous auto precharge will be per formed. illegal = device operation and/or data-integrity are not guaranteed. refreshing h x x x x desel nop(idle after trp) l h h h x nop nop(idel after trp) lh hlx term nop l h l x ba, ca, a8 read/write illegal l l h h ba, ra act illegal l l h l ba, a8 pre/prea illegal l l l h x refa illegal ll ll op-code, mode-add mrs illegal table 15: function truth table current state /cs /ras /cas /we address command action doc # 14-02-045 rev a ecn 01-1118 29 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information abbreviations : h=high level, l=low level, v=valid, x=don?t care note : 1. after cke?s low to high transition to exist self refres h mode. and a time of trc(min) has to be elapse after cke?s low t o high transition to issue a new command. 2. cke low to high transition is asynchronous as if restarts internal clock. a minimum setup time ?tis + one clock? must be satisfied before any command other than exit. 3. power-down and self-refresh can be entered only from the all banks idle state. 4. must be a legal command. table 16: function truth table for cke current state cken-1 cken /cs /ras /cas /we add action self- refreshing hxxxxxxinvalid l h h x x x x exit self-refresh*1 l h l h h h x exit self-refresh*1 l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop(maintain self-refresh) both bank pre- charge power down hxxxxxxinvalid l h h x x x x exit power down*2 l h l h h h x exit power down*2 l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop(maintain power down) all banks idle h h x x x x x refer to function true table h l h x x x x enter power down*3 h l l h h h x enter power down*3 h l l h h l x illegal h l l h l x x illegal h l l l h h ra row(& bank) active h l l l l h x enter self-refresh *3 h l l l l l op code mode register access lxxxxxx refer to current state=power down any state other than listed above h h x x x x x refer to function true table hlxxxxx begin clock suspend next cycle*4 lhxxxxx exit clock suspend next cycle*4 l l x x x x x maintain clock suspend doc # 14-02-045 rev a ecn 01-1118 30 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information timing figure 24: basic timing (setup, hold and access time @bl=2, cl=3) 012345678 /ck ck cke /cs dqs dq high dm command rea da writec trpre tch tcl tck tis tih /ras /cas a 8 /ap ba[1:0] addr /we trpst tdqsq tdqss twpreh twpres tdqsh tdqsl twpst tdstdhtdstdh writeb (a 0~a7,a9~a11) baa ca bab cb bac cc qa1 qa0 hi-z hi-z db 0 db 1 dc 0 dc 1 012345678 /ck ck cke /cs dqs dq high dm command rea da writec trpre tch tcl tck tis tih /ras /cas a 8 /ap ba[1:0] addr /we trpst tdqsq tdqss twpreh twpres tdqsh tdqsl twpst tdstdhtdstdh writeb (a 0~a7,a9~a11) baa ca bab cb bac cc qa1 qa0 qa1 qa0 qa0 hi-z hi-z db 0 db 1 dc 0 dc 1 doc # 14-02-045 rev a ecn 01-1118 31 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information figure 25: multi bank inte rleaving read (@bl=4, cl=3) 0 1 23 4 5678 10 9 /ck ck cke /ras a 8 /ap addr /we dqs dq high ba[1:0] /cas dm command activea activeb rea da readb (a 0~a7,a9~a11) baa bab ra rb ra rb baa ca baa ca /cs trrd qa0 qa1 qa2 qa3 qb0 0 1 23 4 5678 10 9 /ck ck cke /ras a 8 /ap addr /we dqs dq high ba[1:0] /cas dm command activea activeb rea da readb (a 0~a7,a9~a11) baa bab ra rb ra rb baa ca baa ca /cs trrd qa0 qa1 qa2 qa3 qb0 doc # 14-02-045 rev a ecn 01-1118 32 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information figure 26: multi bank inte rleaving write (@bl=4, cl=3) cke /cs a 8 /ap dqs dq high ba[1:0] command /ras 012 3 45 6 78 addr trrd trc dw (a 0~a7,a9~a11) /cas /we trc dw writea activeb writeb baa baa bab bab ra rb ra ca rb cb da0 da1 da2 da3 db 0 db 1 db 2 db 3 dm activea /ck ck tdqssmin cke /cs a 8 /ap dqs dq high ba[1:0] command /ras 012 3 45 6 78 addr trrd trc dw (a 0~a7,a9~a11) /cas /we trc dw writea activeb writeb writea activeb writeb baa baa bab bab ra rb ra ca rb cb da0 da1 da2 da3 db 0 db 1 db 2 db 3 dm activea activea /ck ck tdqssmin doc # 14-02-045 rev a ecn 01-1118 33 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information figure 27: auto precharge after read burst (@bl=8) cke high dm command 0 1 23 4 5 67 8 activea tras (min) trp auto precharge start *1 /ras /cas ba[1:0] baa a 8 /ap addr ca /we baa ra ra (a0~a7,a9~a11) qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 /cs reada /ck ck dqs(cl=3) dq(cl=3) cke high dm command 0 1 23 4 5 67 8 activea tras (min) trp auto precharge start *1 /ras /cas ba[1:0] baa a 8 /ap addr ca /we baa ra ra (a0~a7,a9~a11) qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 /cs reada /ck ck dqs(cl=3) dq(cl=3) doc # 14-02-045 rev a ecn 01-1118 34 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information figure 28: auto precharge after write burst (@bl=4) cke /cas /we dqs twpres twpreh twr trp auto precharge start *1 dq command writea activea high /ras ba[1:0] baa a 8 /ap baa 012345 6 78 /ck ck addr baa ra ra (a 0~a7,a9~a11) /cs da0 da1 da2 da3 dm cke /cas /we dqs twpres twpreh twr trp auto precharge start *1 dq command writea activea high /ras ba[1:0] baa a 8 /ap baa 012345 6 78 /ck ck addr baa ra ra (a 0~a7,a9~a11) /cs da0 da1 da2 da3 dm doc # 14-02-045 rev a ecn 01-1118 35 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information figure 29: normal write burst (@bl=4) cke /cs command writea pre- charge high dqs dq 0 1 23 4 5 67 8 /ck ck baa /ras /cas ba[1:0] a8/ap ca addr /we baa (a 0~a7,a9~a11) twpres twpreh twr da0 da1 da2 da3 dm cke /cs command writea pre- charge high dqs dq 0 1 23 4 5 67 8 /ck ck baa /ras /cas ba[1:0] a8/ap ca addr /we baa (a 0~a7,a9~a11) twpres twpreh twr da0 da1 da2 da3 dm doc # 14-02-045 rev a ecn 01-1118 36 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information figure 30: write interrupted by precharge & dm (@bl=8) cke high dqs twpres twpreh dq command writea twr pre- charge writeb writec tccd 012345 6 78 /cas /we /ras ba[1:0] baa addr ca (a0~a7,a9~a11) /cs a8/ap baa bab bac cc cc db 1 dc 0 dc 1 dc 2 db 0 da4 da5 da6 da7 da3 da1 da2 da0 dm /ck ck cke high dqs twpres twpreh dq command writea twr pre- charge writeb writec tccd 012345 6 78 /cas /we /ras ba[1:0] baa addr ca (a0~a7,a9~a11) /cs a8/ap baa bab bac cc cc db 1 dc 0 dc 1 dc 2 db 0 da4 da5 da6 da7 da3 da1 da2 da0 dm /ck ck doc # 14-02-045 rev a ecn 01-1118 37 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information figure 31: read interrupted by precharge (@bl=8) cke high command reada dqs(cl=3) dq(cl=3) dm pre charge 012345 6 78 /ck ck /ras /cas ba[1:0] baa addr ca /we /cs (a0~a7,a9~a11) a 8 /ap baa qa2 qa3 qa4 qa5 qa0 qa1 cke high command reada dqs(cl=3) dq(cl=3) dm pre charge 012345 6 78 /ck ck /ras /cas ba[1:0] baa addr ca /we /cs (a0~a7,a9~a11) a 8 /ap baa qa2 qa3 qa4 qa5 qa0 qa1 doc # 14-02-045 rev a ecn 01-1118 38 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information figure 32: read interrupted by burst stop & write (@bl=8, cl=3) high command reada dqs dq writeb burst st op 012345 6 78 /ck ck cke /cas /we /ras ba[1:0] addr (a0~a7,a9~a11) /cs a8/ap baa ca baa cb qa5 qa0 qa1 dm db 2 db 3 db 4 db 0 db 1 high command reada dqs dq writeb burst st op 012345 6 78 /ck ck cke /cas /we /ras ba[1:0] addr (a0~a7,a9~a11) /cs a8/ap baa ca baa cb qa5 qa0 qa1 dm db 2 db 3 db 4 db 0 db 1 doc # 14-02-045 rev a ecn 01-1118 39 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information figure 33: read interrupted by read (@bl=8, cl=3) cke high command dqs dq 012345 6 78 /ck ck /cas /we /ras ba[1:0] addr (a0~a7,a9~a11) /cs a8/ap baa ca bab bab dm qb3 qb0 qb1 qb2 qa0 qa1 qb7 qb4 qb5 qb6 reada readb tccd doc # 14-02-045 rev a ecn 01-1118 40 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information figure 34: dm fun ction (@bl=8) only for write 012 nop /ck ck command 345 67 8 nop nop nop nop nop nop nop write dqs dq?s din 0 t dqss t wpreh t wpres din 1 din 2 din 3 din 4 din 5 din 6 din 7 masked by dm=h dm dm 012 nop /ck ck command 345 67 8 nop nop nop nop nop nop nop write dqs dq?s din 0 t dqss t wpreh t wpres din 1 din 2 din 3 din 4 din 5 din 6 din 7 masked by dm=h dm 012 nop /ck ck command 345 67 8 nop nop nop nop nop nop nop write dqs dq?s din 0 t dqss t wpreh t wpres din 1 din 2 din 3 din 4 din 5 din 6 din 7 masked by dm=h dm dm cke high command dqs dq writea 0 1 23 4 5 67 8 /ck ck /ras /cas ba[1:0] baa addr ca /we /cs (a0~a7,a9~a11) a 8 /ap twpres twpreh da3 da0 da1 da2 da7 da4 da5 da6 dm tdh tds tds tdh cke high command dqs dq writea 0 1 23 4 5 67 8 /ck ck /ras /cas ba[1:0] baa addr ca /we /cs (a0~a7,a9~a11) a 8 /ap twpres twpreh da3 da0 da1 da2 da7 da4 da5 da6 dm tdh tds tds tdh doc # 14-02-045 rev a ecn 01-1118 41 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information figure 35: power up sequenc e & auto refresh (cbr) dqs dq dm hig h - z hig h - z hig h inputs must be stable fo r 200us precharge command all bank emrs command precharge command all bank mrs dll reset command 1st a uto refresh command 2nd auto refresh command mode register set c ommand any command t rp t mrd t mrd trfc trfc t rp t mrd minimum of 2 refresh cycles are required cke /cas addr /we /cs (a0~a7,a9~a11) a 8 /ap 0 1234 56 78 /ck ck /ras ba[1:0] ba[1:0] high dqs dq dm hig h - z hig h - z hig h inputs must be stable fo r 200us precharge command all bank emrs command precharge command all bank mrs dll reset command 1st a uto refresh command 2nd auto refresh command mode register set c ommand any command t rp t mrd t mrd trfc trfc t rp t mrd minimum of 2 refresh cycles are required cke /cas addr /we /cs (a0~a7,a9~a11) a 8 /ap 0 1234 56 78 /ck ck /ras ba[1:0] ba[1:0] high doc # 14-02-045 rev a ecn 01-1118 42 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information figure 36: mode register set cke high dqs dq dm hig h - z hig h - z hig h precharge all bank command mode register set c ommand any command t rp t mrd /cas addr /we /cs (a 0~a7,a9~a11) a 8 /ap 0 1234 56 7 8 /ras ba[1:0] /ck ck cke high dqs dq dm hig h - z hig h - z hig h precharge all bank command mode register set c ommand any command t rp t mrd /cas addr /we /cs (a 0~a7,a9~a11) a 8 /ap 0 1234 56 7 8 /ras ba[1:0] /ck ck doc # 14-02-045 rev a ecn 01-1118 43 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information ibis : i/v characteristics for input and output buffers reduced output driver characteristics. 1. the nominal pulldown v-i curve for ddr sdram devices will be within the inner bounding lines of the v-i curve of below figure. 2. the full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of below figure 3. the nominal pullup v-i curve for ddr sdram devices will be within the inner bounding lines of the v-i curve of below figure. 4. the full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of below figure 5. the full variation in the ratio of the maximum to mini mum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to vddq/2 6. the full variation in the ratio of the nominal pullup to pulldown current should be unity 0%, for device drain to source voltages from 0 to vddq/2 vout (v) iout (ma) maximum typical high typical low minimum 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 0.1 0.6 1.1 1.6 2.1 vout (v) iout (ma) maximum typical high typical low minimum -110.0 -100.0 -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 0.1 0.6 1.1 1.6 2.1 doc # 14-02-045 rev a ecn 01-1118 44 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information temperature (ambient) typical 25 c minimum70c maximum 0c vdd/vddq typical 2.50v / 2.50v minimum 2.375v / 2.375v maximum2.625v / 2.625v the above characteristics are specified under be st, worst and normal process variation/conditions table 17: pulldown and pu llup iv characteristics voltage (v) pulldown current(ma) pullup current(ma) typical low typical high min max typical low typical high min max 0.1 3.3 3.7 2.5 4.8 -3.3 -4.1 -2.5 -4.9 0.2 6.6 7.3 5.0 9.4 -6.6 -7.8 -5.0 -9.7 0.3 9.8 10.9 7.4 14.0 -9.8 -11.4 -7.4 -14.5 0.4 13.0 14.4 10.0 18.3 -12.9 -14.9 -10.0 -19.2 0.5 16.1 17.8 12.4 22.6 -16.1 -18.4 -12.4 -23.9 0.6 18.7 21.1 14.9 26.7 -18.5 -21.9 -14.9 -28.4 0.7 21.3 23.9 17.4 30.7 -20.5 -25.3 -17.4 -32.9 0.8 23.6 26.9 19.9 34.1 -22.2 -28.7 -19.5 -37.3 0.9 25.6 29.8 21.4 37.7 -23.6 -32.1 20.6 -41.7 1.0 27.7 32.6 23.0 41.2 -24.8 -35.4 -20.9 -46.0 1.1 29.2 35.2 24.2 44.5 -25.8 -38.6 -21.1 -50.7 1.2 30.3 37.7 25.0 47.7 -26.6 -41.9 -21.2 -54.3 1.3 31.3 40.1 25.4 50.7 - 27.0 45.2 -21.3 -58.4 1.4 32.0 42.4 25.6 53.5 -27.2 -48.4 -21.4 -62.4 1.5 32.5 44.4 25.8 56.0 -27.4 -51.6 -21.5 -66.4 1.6 32.7 46.4 25.9 58.6 -27.5 -54.7 -21.6 -70.4 1.7 32.9 48.1 26.2 60.6 -27.6 -57.8 -21.7 -73.8 1.8 33.2 49.8 26.4 62.6 -27.7 -60.7 -21.8 -77.8 1.9 33.5 51.5 26.5 64.6 -27.8 -64.1 -21.8 -81.3 2.0 33.8 52.5 26.7 66.6 -27.9 -67.0 -21.9 -84.7 2.1 33.9 53.5 26.8 68.3 -28.0 -69.8 -21.9 -88.1 2.2 34.2 54.5 26.9 69.9 -28.1 -72.7 -22.0 -91.6 2.3 34.5 55.0 27.0 71.5 -28.2 -75.6 -22.0 -95.0 2.4 34.6 55.5 27.0 72.9 -28.2 -78.4 -22.1 -97.0 2.5 34.9 56.0 27.1 74.1 -28.3 -81.3 -22.2 -101.3 doc # 14-02-045 rev a ecn 01-1118 45 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information figure 37: package dimens ions (144-balls fbga) a1 index mark 12.0 12.0 doc # 14-02-045 rev a ecn 01-1118 46 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. nt5ds4m32eg advance information ? 2005 nanoamp solutions, inc. all rights reserved. nanoamp solutions, inc. ("nanoamp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. nanoamp does not convey any license under its patent rights nor the rights of others. charts, drawings and schedules contained in this data sheet are provided for illustration pur- poses only and they vary depending upon specific applications. nanoamp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does nanoamp ass ume any liability arising out of the application or use of any product or circuit described herein. nanoamp does not authorize use of its products as critical components in any application in which the failure of the nanoamp product may be expected to result in significant injury or de ath, including life support systems and critical medical instrumen t. revision history revision date change description a march 2005 initial release |
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